Adiabatic CAM

I helped design an adiabatic Content Addressable Memory (CAM) for low power applications. CAMs are gaining increased importance in the industry due to their parallel matching property. This property makes them useful in applications such as networking where a quick search is needed in routing tables and in CACHES. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry without sacrificing speed or memory density. CAM structure is similar to that of a conventional SRAM but has additional circuitry for its compare operation. The compare circuit is a major source of power consumption. The energy dissipation is majorly caused by the charging and discharging of the node capacitance in the design. By applying adiabatic switching to a CAM the energy dissipation in the match-line where charging and discharging is done can be drastically reduced. Further, for this specific design, the circuitry for the matchline was setup so that no precharging was necessary and the matchline only charged on matches and was inactive on mismatches.

Besides using an adiabatic source on the match lines of each bit to conserve power, standard power conservation methodologies were also incorporated such as sleeper transistors, dynamic logic, and optimal frequency and power trade-offs. The finished design reduced power 30% from a typical CAM.

Final schematic layout: